S1C33L26 cmos 32-bit application specific controller 32-bit risc cpu core (epson s1c33 pe core) (max. 60 mhz operation) 34kb ram (including cache and vram) programmable operating clock using pll (division ratio: 1/1 1/10, multiplication ratio: x1 x16) dsp function (multiplier/ divider) 1kb instruction cache and 1kb data cache graphics engine (ge) drawing objects, image data block transfer, drawing effects word boundary commands (variable length) are provided for drawing control and commands list. lcd controller supports 1/2/4/8/12/16 and 24 bpp (16m-color) tft color panel supports 1/2/4/8/12 bpp cstn,1/2/4 bpp mono-stn panel ivram (qvga: 320 x 240 2bpp) supports up to 16m-color lcd controlle r with external sdram/sram as vram. two-image overlay display via the pi cture-in-picture plus function brightness/gray scale control via the mono display lut (look up table with 16 4 bits), or palette control via the color display lut (look up table ram with 256 16 bits) 8-ch. dma controller burst control sdram controller 1-ch. x 16-bit audio pwm timer 2-ch. x 16-bit pwm timer, 8-ch. x 8-bit timer 1-ch. universal serial i/f (uart/spi/i2c) 1-ch. universal serial i/f with serial or parallel lcd interface 2-ch. sio with fifo i 2 s bus interface (16-bit format) remote controller circuit (remc) 6-ch. 10-bit adc for analog input usb fs(12mbps) function controller (fifo 1kb) rtc and 16-byte battery backup ram with separated rtcv dd descriptions the S1C33L26 is a 32-bit application specific risc controller that features ext ensive peripheral circuits such as an enhanced drawing graphics module, gpio ports, serial interf ace modules, a usb module, pwm generators, and an a/d converter. it is suitable for applications that require a high-resolution lcd disp lay, e.g. control panels on oa/fa equipment and intelligent remote controllers. the S1C33L26 incorporates an lcd controlle r and vram supporting four-level gray scale qvga display in single-chip. adding an external sdram expands this capability into a higher re solution and with more display able colors (e.g., 64k-color vga display). an lcd driver interface with dma function is also implemented allowing efficient data transfer to lcd modules that include a built-in vram lcd driver . in addition, the embedded graphics engine (g e) provides rich graphic features, such as drawing functions for dots, stra ight lines, triangles, rectangles, and circle s, resizing, and rotation that can be used simply by calling commands. the ge also supports drawing of lossless compressed image data; this makes it possible to reduce cpu load and image data rom size. as for dsp functions, a 32-bit 32-bit multiplier (mul) and a 16- bit 16-bit divider (div) are implemented. these functions help reduce cpu load for adpcm audio data playback processi ng. also the embedded i2s interface module is used to connect an external audio dac. the S1C33L26 has adopted the epson soc (syste m on chip) design technology using 0.18 m low power cmos process to install these features.
S1C33L26 2 seiko epson corporation ? features z technology ? 0.18 m al-4-layers mixed analog low power cmos process technology z cpu ? epson original c33 pe 32-bit risc cpu-core ? maximum operating frequency: 60 mhz (36 mhz in sdram double frequency mode) ? internal two-stage pipeline ? instruction set: 125 inst ructions (16-bit fixed length) ? dual amba bus system for cpu and ge z dsp ? multiplier (mul) - 32 32 bits (seven cycles) or 16 16 bits (five cycles) ? divider (div) - 16 16 bits (18 cycles) z internal memories ? iram (internal ram) - 12k bytes ? ivram (internal vram) - 20k bytes - configurable as a 32k-byte general-pur pose ram sequentially addressed with iram ? cache ram - 1k bytes (instruction cache ram) - 1k bytes (data cache ram) - usable as a general-purpose ra m when not used as cache ram ? dstram (dma descriptor ram)/lutram (look-up table ram) - 512 bytes (can exclusively be used as either dstram or lutram.) - dma descriptor ram for storing dma control table (128 32 bits) - color look-up table ram for lcdc (256 16 bits) 16 bits = (r: 5 bits, g: 6 bits, b: 5 bits) - the dma control table can be located in the ivram or an external ram when this ram is used for lcdc color look-up table. ? bbram (battery backup ram) - 16 bytes - the ram contents can be maintained while the system pow er is off using the separated power supply for rtc. z input clock ? high-speed clock (osc3) - maximum input clock frequency: 48 mhz - internal oscillator circuit (crystal or ceramic resonator) or external clock input ? low-speed clock (osc1) - 32.768 khz (typ.) clock for rtc and low-power operations - internal oscillator circuit (crystal resonator) or external clock input z cache controller (ccu) ? 1k-byte instruction cache and 1k-byte data cache with a four-way associative frame stru cture (four frames/way, four lines/frame, four words/line) ? lru replacement algorithm ? automatic lock function during debug mode and the interrupt process of specified priority ? the instruction cache ram and data cache ram can be used as a general-purpose ram w hen the cache function is disabled. z dma controller (dmac) ? eight channels of table dma ? supports table reloading and low-priority channel pausing functions. ? trigger sources - usi (spi/uart) - usil (spi/uart/built-in ram lcd interface) - fsio (asynchronous/synchronous) - i2s - 16-bit audio pwm timer (t16p) - a/d converter (adc10) - i/o ports (gpio) - usb function controller (usb) - 16-bit pwm timer (t16a5) - software z graphics engine (ge) ? object drawing - shapes with width: straight lines (vertical, hor izontal, and sloped lines), rectangle frames, and circle rings
S1C33L26 seiko epson corporation 3 - solid shapes: points, triangles, rectangles, quadrilaterals, circles - texts with a font specified - compressed image (original run-length encoding) ? image data block transfer - rectangle area copy within vram - data copy between vram and other memory ? drawing effects - clip drawing - line width setting - drawing color setting with transparency effect - fill/mesh/rewrite/xor - color conversion with palette/color depth conversion - resize/repeat/rotation (texts/compressed image) ? word boundary commands (variable l ength) for drawing control and commands list. z sram controller (sramc) ? allows direct connection of sram, rom, and flash memories. ? 26-bit address bus and 8/16-bit selectable data bus ? up to six chip enable signals are available to connect external devices. ? up to 64m-byte (a[25:0]) address sp ace is accessible with each chip enable signal. ? programmable bus access wait cycle (0 to 15 cycles) ? supports little endian access. ? memory mapped i/o ? supports both a0 and bs (bus strobe) type devices. ? supports external wa it request via the #wait pin. z sdram controller (sdramc) ? supports sdram direct interface. (max. 72 mhz sdram clock) ? supports only sdram devices with 16-bit data bus. - minimum configuration: 16m bits (2mb), 16-bit sdram 1 - maximum configuration: 512m bits (64mb), 16-bit sdram 1 ? cas latency: one, two, or three programmable ? supports burst and single read/write operations. ? equipped with a two-stage 32-bit dqb (data queue buffer). ? supports up to four sdram banks and bank active mode. ? built-in 12-bit auto-refresh counter ? intelligent self-refresh function for low power operation ? arbitrates ownership of the exte rnal bus between the cpu, dmac, lcdc, and ge. z clock management unit/oscillators/pll (cmu) ? selects the system clock source (osc3, pll, osc1). ? turns the osc3 and osc1 oscillator circuits on and off. ? controls frequency multiplicat ion rate of the pll (1 to 16). ? controls clocks according to the standby mode (sleep and halt). ? controls the external clock. ? controls clock supply to the core and peripheral modules. ? osc3 oscillator circuit - crystal oscillation: 5 mhz min. to 48 mhz max. - ceramic oscillation: 5 mhz min. to 48 mhz max. - external clock input: 5 mhz min. to 48 mhz max. * a 48 mhz clock source with 0.25% of accu racy should be connected for using the usb function. * before using a ceramic resonator, please be sure to contact murata manufacturing co., ltd. for further information on conditions of use for ceramic resonators. ? pll - pll input frequency: 5 mhz min. to 50 mhz max. (osc3 1, 1/2, 1/3, ... 1/9, 1/10) - pll output frequency: 20 mhz min. to 72 mhz max. - multiplication rate: 1, 2, 3, ... 15, 16 ? osc1 oscillator circuit - crystal oscillation: 32.768 khz typ. - external clock input: 32.768 khz typ. z interrupt controller (itc) ? five non-maskable interrupts ? 31 maskable interrupts (including four software interrupts) z 16-bit audio pwm timer (t16p) ? one channel of 16-bit time r/counter with pwm output function ? three bit division modes are provided. (10 bits + 6 bits, 9 bits + 7 bits, 8 bits + 8 bits) ? supports 8, 16, 22.05, 32, 44.1, and 48 khz sampling rates. ? audio pwm function supporting 8-bit and 16-bit pcm data (mono) ? can output monophonic sound without using an external dac (external re sistors and capacitors are required). ? supports fine mode to control pulse widths with high accuracy. ? supports a digital volume control function. ? can generate two types of compare-match interrupts.
S1C33L26 4 seiko epson corporation ? supports dma transfer. z 8-bit timers (t8, t8f) ? t8f: four channels of 8-bit timer with fine mode (presettable down counter) t8: four channels of 8-bit timer without fine mode ? clocks generated with the counter under flow can be output to internal devices. - the t8f ch.0 can be used as the usi clock generator. - the t8f ch.3 can be used as the usil clock generator. - the t8f ch.2 can be used to trigger the adc10. ? each timer can generate underflow interrupts. z 16-bit pwm timer (t16a5) ? two channels of 16-bit timer with a counter capture/ comparison functions ? each channel has built-in two comparison/capture data buffers. ? can generate compare/capture interrupts. ? supports dma transfer. z watchdog timer (wdt) ? 30-bit watchdog timer to generate an nmi or a reset ? programmable watchdog timer overflow period (nmi or reset interrupt period) ? the watchdog timer overflow signal can be output outside the ic. z real time clock (rtc) ? contains time counters (seconds, minutes, and hours) and calendar counters (days, day s of the week, months, and years). ? 24-hour or 12-hour mode can be selected. ? operates with an independent power supply (rtcvdd) se parated from system power (operable while the system power is off). ? provides the wakeup output pin and #stby input pin to control standby mode. ? can generate periodic interrupts. z universal serial interface (usi) ? multi-serial i/o that can be used as a uart, spi, or i2c module ? contains 1-byte receive data buffer and 1-byte transmit data buffer. ? uart mode - character length: 7 or 8 bits - parity mode: even, odd, or no parity - stop bit: 1 or 2 bits (start bit: 1 bit fixed) - supports both msb first and lsb first modes. - parity error, framing error, and overrun error detectable - can generate receive buffer full, transmit buffer empty, and receive error interrupts. - supports dma transfer. ? spi mode - supports both master and slave modes. - data length: 8 or 9 bits (master mode), 8 bits fixed (slave mode) - supports both msb first and lsb first modes. - data transfer timing (clock phase and polarity variations) is selectable from among 4 types. - receive data mask function is available. - can generate receive buffer full, transmit buffer empty, and overrun error interrupts. - supports dma transfer. ? i2c mode - supports both master (single master only) and slave modes. - 7-bit addressing mode (10-bit addressing is possible by software control.) - supports clock stretch/wait functions. - can generate start/stop, data transfer, ack/ nak transfer, and overrun error interrupts. z universal serial interface with built-in ram lcd interface (usil) ? multi-serial i/o that can be used as a ua rt, spi, i2c, or built-in ram lcd interface module ? contains 1-byte receive data buffer and 1-byte transmit data buffer. ? uart mode - character length: 7 or 8 bits - parity mode: even, odd, or no parity - stop bit: 1 or 2 bits (start bit: 1 bit fixed) - supports both msb first and lsb first modes. - parity error, framing error, and overrun error detectable - can generate receive buffer full, transmit buffer empty, and receive error interrupts. - supports dma transfer. ? spi mode - supports both master and slave modes. - data length: 8 bits fixed - supports both msb first and lsb first modes. - data transfer timing (clock phase and polarity variations) is selectable from among 4 types. - receive data mask function is available. - can generate receive buffer full, transmit buffer empty, and overrun error interrupts. - supports dma transfer.
S1C33L26 seiko epson corporation 5 ? i2c mode - supports both master (single master only) and slave modes. - 7-bit addressing mode (10-bit addressing is possible by software control.) - supports clock stretch/wait functions. - can generate start/stop, data transfer, ack/ nak transfer, and overrun error interrupts. ? lcd spi mode - data length is configurable for 8 bits, 16 bits, 18 bits (4 data format) and 24 bits + cmd bit. - cmd bit or a0 is selectable. - data transfer timing (clock phase and polarity variations) is selectable from among 4 types. - can generate transmit buffer empty interrupts. - supports dma transfer. ? lcd parallel interface mode - provides 8-bit data bus, #cs, #rd, #wr and a0 control signals. - supports byte read/write access mode only. - can generate transmit buffer empty and receive buffer full interrupts. - supports dma transfer for bot h data transmission and reception. - access timings can be controlled using t8f. the setup cycl e (1 to 4), hold cycle (1 to 4), and wait cycle (1 to 16) are configurable. z serial interface with fifo (fsio) ? two channels of clock synchronous/asynchronous serial interface ? contains fifo data buffers (4-byte receive data buffer and 2-byte transmit data buffer are available for each channel). ? supports irda1.0-equivalent communications by software control or using an external irda driver. ? contains a baud-rate generator (12-bit programmable timer). ? can generate receive buffer full, transmi t buffer empty, and receive error interrupts. ? supports dma transfer. z i 2 s bus interface (i2s) ? supports universal audio i 2 s bus interface. ? contains a 16-byte transmit fifo (16 bits 2 channels 4) ? i 2 s output: one channel ? resolution: 16 bits (pcm data output format) ? operates as master t hat generates the bit clock, word-s elect signal, data and master clock. ? clock polarity and data shift direction (m sb first/lsb first) are software configurable. ? can generate i 2 s fifo empty interrupts. ? supports dma transfer. z card interface (card) ? generates 8-bit or 16- bit nand flash interface signals. ? the ecc and edc functions should be implemented in the application program. z infrared remote controller (remc) ? outputs a modulated carrier signal and inputs remote control pulses. ? embedded carrier signal generator and data length counter ? can generate counter underflow interrupts for data tr ansmission and input rising/falling edge detection interrupts for data reception. z lcd controller (lcdc) ? supports stn lcd panels with 4/8-bit data lines or tft lcd panels with up to 24-bit data lines. ? supports generic panel resolutions up to vga, such as 640 480 pixels (vga) and 320 240 pixels (qvga) (can be configured according to the panel used). ? supports up to 16m-color (for color tft), 4k-color (f or color stn), and 16-level gray scale (for monochrome stn) display modes. ? typical display configuration when the internal vram (20kb) is used - 320 240 pixels, 2 bpp (4-level gray scale display) ? display configuration when an external memory is used - 320 240 pixels, 16 bpp (qvga 64k-colors display) - 400 240 pixels, 16 bpp (wqvga 64k-colors display) - 640 480 pixels, 16 bpp (vga 64k-colors display) ? two-image overlay display via the picture-in-picture plus function ? brightness/gray scale control via the mono display lut (look up table with 16 4 bits), or palette control via the color display lut (look up table ram with 256 16 bits) ? virtual display function to handle images with a differ ent resolution from the lcd panel (any area in the virtual screen can be displayed on the lcd.) z a/d converter (adc10) ? 10-bit a/d converter with up to six analog input channels ? conversion time: 10 s min. (when 2 mhz input clock is selected) 1,250 s max. (when 16 khz input clock is selected) ? can generate conversion comp letion and data overwrite interrupts. z usb function controller (usb) ? supports usb2.0 full speed (12m bps) mode. ? supports auto negotiation function. ? supports control, bulk, isochronous and interrupt transfers.
S1C33L26 6 seiko epson corporation ? scratchable variable number of bulk end points ? embedded 1k-byte programmable fifo ? can generate usb interrupts. ? supports dma transfer. z general-purpose i/o ports (gpio) ? maximum 71 i/o ports and six input ports are available (144-pin package). ? can generate maximum 16 input interrupts from 64 i/o ports. ? supports dma transfer. * the gpio ports are shared with other peripheral func tion pins (usi, pwm etc.). t herefore, the number of gpio ports depends on the peripheral functions used. z operating voltage ? hvdd (i/o power voltage) 2.7 v to 3.6 v (3.3 v typ.) or 3.0 v to 3.6 v (3.3 v typ.) when the usb module is used. ? avdd (analog power voltage) 2.7 v to 3.6 v (3.3 v typ.) or 3.0 v to 3.6 v (3.3 v typ.) ? lvdd (core/internal logic power voltage) 1.65 v to 1.95 v (1.8 v typ.) or 1.7 v to 1.9 v (1.8 v typ.) when a ceramic resonator is used. ? pllvdd (pll power voltage) 1.65 v to 1.95 v (1.8 v typ.) or 1.7 v to 1.9 v (1.8 v typ.) when a ceramic resonator is used. ? rtcvdd (rtc/bbram power voltage) 1.65 v to 1.95 v (1.8 v typ.) or 1.7 v to 1.9 v (1.8 v typ.) when a ceramic resonator is used. * lvdd = pllvdd = rtcvdd the S1C33L26 does not support 5 v tolerant i/o. z operating temperatures ? -40 to 85c ? 0 to 70c when the usb modul e and a ceramic resonator are used. z power consumption ? during sleep: 2.6ua (typ.) rtc: on 1.6ua (typ.) rtc: off ? during halt: 4.2ma (typ.) when 48mhz osc is used. all peripheral clocks: off ? during execution: 22ma (typ.) when 48m hz osc is used with cpu in normal operating state. all peripheral clocks: off 40ma (typ.) when 48mhz osc is used with cpu in normal operating state and ge in idle state. *i/o current is not included. * power consumption can be reduced by contro lling the clocks through the clock management unit (cmu). z shipping form ? die form ? plastic package: tqfp15-128pin tqfp24-144pin pfbga12u-180
S1C33L26 7 ? block diagram semiconductor operations division ic sales department ic international sales group 421-8 hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 http://www.epson.jp/device/semicon_e/ epson semiconductor website document code: 411692100 first issue jan, 2010 in j apan notice: no part of this material may be reproduced or duplicated in any fo rm or by any means without the written permission of seiko ep son. seiko epson reserves the right to make c hanges to this material without notice. se iko epson does not assume any liability of a ny kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, furt her, there is no representation that this material is app licable to products requiring high level reliab ility, such as, medical products. moreo ver, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that any thing made in accordance with this material will be free from any patent or copy right infringement of a third party. this material or portio ns thereof may contain technology or the subject relati ng to strategic products under the control of the foreign exchange and foreign trade la w of japan and may require an export license from the ministry of economy, trade and industry or other approval from another government ag ency. all brands or product names mentioned herein are trademarks and/ or registered trademarks of t heir respective companies. ? seiko epson corporation 2010, all rights reserved div c33 pe core dmac ccu ar ea 0 ar e 3 cach e (2k bytes) iram (12k bytes) ge lcdc lut 256 half-words bus controller sram c sdramc sapb bridge dst ra m (128 words) misc cmu it c gpio pmux usi usil fsio (2ch.) usb psc wdt t8f (4ch) t8 (4ch) t16a5 (2ch) t16p adc10 i2s rem c lc dc (reg.) dmac (reg.) sdramc (reg.) sramc (reg.) ccu (reg.) ge (reg.) rt c bbr am (16 by tes) s1 c33 l26 iram (20k bytes) ivram (20k bytes) arbiter arbiter ivr am i /f ahb-1 ahb-2 external bus rtcv dd sapb software switch software switc h div c33 pe core dmac ccu ar ea 0 ar e 3 cach e (2k bytes) iram (12k bytes) ge lcdc lut 256 half-words bus controller sram c sdramc sapb bridge dst ra m (128 words) misc cmu it c gpio pmux usi usil fsio (2ch.) usb psc wdt t8f (4ch) t8 (4ch) t16a5 (2ch) t16p adc10 i2s rem c lc dc (reg.) dmac (reg.) sdramc (reg.) sramc (reg.) ccu (reg.) ge (reg.) rt c bbr am (16 by tes) s1 c33 l26 iram (20k bytes) ivram (20k bytes) arbiter arbiter ivr am i /f ahb-1 ahb-2 external bus rtcv dd sapb software switch software switc h
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